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Novel data storage for H.264 motion compensation: system architecture and hardware implementation

Elena Matei1*, Christophe van Praet1, Johan Bauwelinck1, Paul Cautereels2 and Edith G de Lumley2

Author Affiliations

1 Intec_design IMEC Laboratory, Ghent University, Sint Pietersnieuwstraat 41, 9000-Ghent, Belgium

2 Alcatel Lucent-Bell, Copernicuslaan 50, Antwerpen, Belgium

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EURASIP Journal on Image and Video Processing 2011, 2011:21  doi:10.1186/1687-5281-2011-21

Published: 19 December 2011


Quarter-pel (q-pel) motion compensation (MC) is one of the features of H.264/AVC that aids in attaining a much better compression factor than what was possible in preceding standards. The better performance however also brings higher requirements for computational complexity and memory access. This article describes a novel data storage and the associated addressing scheme, together with the system architecture and FPGA implementation of H.264 q-pel MC. The proposed architecture is not only suitable for any H.264 standard block size, but also for streams with different image sizes and frame rates. The hardware implementation of a stand alone H.264 q-pel MC on FPGA has shown speeds between 95.9 fps for HD1080p frames, 229 fps for HD 720p and between 2502 and 12623 fps for CIF and QCIF formats.

motion compensation; quarter-pel; address; memory; H.264 decoder; FPGA